1. Field of the Invention
The present invention relates to a driving method for liquid crystal display (LCD), and more particularly to a driving method for liquid crystal display wherein a low power consumption is achieved by multi-phase charging sharing.
2. Description of the Prior Art
FIG. 1 shows a typical active matrix LCD. The LCD 100 includes a matrix of rows and columns of display cells. Each display cell includes a TFT (thin film transistor) 104 on an upper substrate 102, wherein the voltage on a source line 108 is coupled to a pixel electrode 105 and charges a storage capacitor (not shown) connected thereto when the TFT 104 being turned on by the voltage on a gate line 107 during a scan period. Each storage capacitor helps to hold the voltage on the pixel electrode 105 when the TFT 104 is turned off beyond the scan period. The voltages on the gate lines 107 and source lines 108 are respectively generated by a gate driver 110 and source driver 106. Besides, a common electrode 112 is disposed on a lower substrate 116 facing the upper substrate 102. A common voltage driver 114 provides a common voltage to the common electrode 112. Thus, molecules of a liquid crystal layer (not shown) sealed between the upper and lower substrates are rotated in response to voltage differences between the source and common electrodes, which determines the brightness or/and color of each display cell.
FIG. 2 shows an equivalent circuit of the matrix of the display cells in the LCD shown in FIG. 1. The same elements in FIGS. 1 and 2 refer to the same symbols for clarity. In each of the display cells, a switch 208 is coupled between the source line 108 and one end of a capacitor 202, and controlled by the voltage signal on the gate line (not shown). The other end of the capacitor 202 is coupled to the common electrode 112. The switch 208 is formed by the TFT 104 shown in FIG. 1 while the capacitor 202 results from the parallel connection of the storage capacitor with a capacitor formed by the pixel electrode 105, liquid crystal (LC) layer and the common electrode 112. In each column of the display cells, a parasitic capacitor 302 is formed between the common electrode 112 and the source line 108.
FIG. 3 shows waveforms of a common and source voltage respectively on the common electrode 112 and source line 108 of one of the display cells shown in FIG. 2 during three consecutive scan periods in a traditional line inversion driving method. The common voltage Vcom is alternately pulled up and down to the high common voltage level VCOMH and the low common voltage level VCOML at each transition of scan periods. The transition period D1 starts from the middle of the first scan period and ends at the middle of the second scan period while the transition period D2 starts from the middle of the second scan period and ends at the middle of the third scan period. The voltages VCOMH and VCOML are provided by directly pumping a power supply voltage VCI up to 2VCI or down to −VCI through a DC/DC pumping circuit, wherein the power supply voltage is derived from a current source driver. The source voltage Vs is pulled by the (data) signal on the source line 108 to corresponding levels for generation of desired voltage differences +Vb, −Va and +Vc between the source and common electrodes of the display cell respectively during the three scan periods.
The power consumption P, resulting from each scan period transition of one display cell, of the source or common voltage driver is VDD×I, where VDD is the voltage supplied by the source or common voltage driver, and IAVG is the average current drawn from the source or common voltage driver during the transition period D1 or D2 (having the same length of the scan period). Since the equivalent load of each display cell is dominated by the parasitic capacitor Cload, the average current IAVG is approximately equal to the current flowing through the parasitic capacitor Cload and is derived by the equation:IAVG=Cload×Vw×F  (1)where Vw is the difference between the voltages across the parasitic capacitor Cload before and after the transition, and F is the scan rate (reciprocal of one scan period). Further, the voltage difference Vw is derived by the equation:Vw=VPOS+|VNEG|  (2)where VPOS is the positive one of the voltages across the parasitic capacitor Cload before and after the transition, and the VNEG is the negative one. Therefore, the power consumption P is derived by the following equation:P=VDD×Cload×(VPOS+|VNEG|)×F  (3)Accordingly, during the transition period D1, the power consumption is 2VCI×Cload×(Va+Vb)×F. During the transition period D2, the power consumption is 3VCI×Cload×(Va+Vc)×F. Thus, for the scan period starting from the middle of the transition period D1 and ending at the middle of the transition period D2, the average power consumption Ptotal is derived by the equation:Ptotal=½×2VCI×Cload×(Va+Vb)×F+½×3VC1×Cload×(Va+Vc)×F  (4)
However, such a power consumption is relatively large. A power-saving driving method is necessary for improvement of the display device.